module top_module(
input clk,
input in,
input reset,
output out); //
parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;
reg [1:0]state,next_state;
// State transition logic
always@(*)begincase(state)A:beginnext_state=(in)?B:A;endB:beginnext_state=(in)?B:C;endC:beginnext_state=(in)?D:A;endD:beginnext_state=(in)?B:C;endendcase
end
// State flip-flops with synchronous reset
always@(posedge clk)beginif(reset)beginstate<=A;endelse beginstate<=next_state;end
end
// Output logic
assign out=(state==D)?1:0;
endmodule